Low on-resistance (RON) metal-oxide semiconductor (MOS) transistors are desirable for their low power loss and ability to conduct high currents. A cellular array of vertical double-diffused MOS (VDMOS) transistors can be made to have a very low [RON*Area] product (Ω mils2). This is partly because no top surface area is used to form drain regions, which allows a high density of transistor to be connected in parallel and a source metal layer to substantially cover the top surface of the transistor structure. The large source metal width provides a low metal resistance, while the high density of the transistors connected in parallel provides a very low transistor on-resistance between the source and drain regions.
For integrated circuit (IC) applications, however, forming N-channel and P-channel VDMOS transistors in the same substrate is impractical. Additionally, it may be desirable to connect the body of a transistor to a separate biasing voltage, which is not possible with cellular VDMOS transistors. Other limitations also exist with VDMOS transistors when formed in an IC, such as a high drain-to-substrate capacitance and a large overhead associated with bringing the drain up to the top surface of the substrate to interconnect the VDMOS transistors with other circuitry on the same substrate. Moreover, a VDMOS transistor formed on a discrete device may require a large overhead to terminate the outer edges, contain a large parasitic junction gate field-effect transistor (JFET), and have a high epitaxial drain resistance.
Problems are also associated with forming P-channel discrete VDMOS transistors. Specifically, it is tough to fabricate a low resistivity P+ substrate, there is a need for a thicker P epitaxial layer to allow for P autodoping by the substrate, and it is difficult to control the resistivity of the P epitaxial layer.
In situations where the drawbacks of a VDMOS transistor prevent its use, lateral MOS transistors have been used. U.S. Pat. No. 5,355,008, entitled “Diamond Shaped Gate Mesh for Cellular MOS Transistor Array,” which is hereby incorporated in its entirety for all purposes, discloses a lateral transistor that has a [RON*Area] product comparable to that of vertical transistors. The lateral transistor disclosed employs a polysilicon gate mesh to separate the source and drain regions of the transistor.
Although the gate mesh lateral transistor is ideal under circumstances where a vertical transistor is impractical, it can be even better. For instance, since currents do not flow through the intersections in the gate mesh between two source regions or between two drain regions, those areas of the polysilicon could be put to better use. In addition, as a result of the proximity effect of masking, the length of the channels between a source region and a drain region may be larger than necessary. Further, when the contact of a source or drain region is defective, that region is no longer effective because the region is completely enclosed by the polysilicon gate mesh.
Accordingly, there is a need for a lateral transistor that better utilizes the intersections in the polysilicon gate mesh between two source/drain regions, improves the length of channels between source regions and drain regions, and is capable of using a region even after the contact for the region becomes inoperable without sacrificing the advantages achieved by the gate mesh lateral transistor. The present invention addresses such a need.